A big roadblock in learning verification is that it is difficult to get access to tools that implement constraint random verification and UVM. There are free tools like EDA Playground but this needs a non free email and constant internet access. Questa/Model sim does not support randomisation in the free version. Open source tools do not support all the language constraints.
The only free tool that I have found that is able to do this is the Xilinx Vivado. Registering on the website will give you access to the free version of the tool. Below I explain the steps needed to implement this in a Linux environment, I do not have access to a windows system and thus cannot verify that this works on a Windows environment.
Tip: Vivado 2020 has support for UVM and is smaller in size when compared to the latest versions, so using it might be good.
Step 1 - Locate the binaries
Navigate to the installation of the Vivado installation in your disk, in my case it is “/opt/Xilinx/Vivado/2020.1/bin/”
The binaries that are required by us are:
xvlog
xelab
xsim
Step 2 - Create aliases
It is cumbersome to define the full path of these binaries each time. One can use either symbolic links or aliases for this. I prefer using aliases over symbolic links for this purpose. Use appropriate bash or zsh commands based on the terminal you use.
$ cd
$ touch .aliases
$ nano .aliasesalias xvlog="/opt/Xilinx/Vivado/2020.1/bin/xvlog"
alias xsim="/opt/Xilinx/Vivado/2020.1/bin/xsim"
alias xtclsh="/opt/Xilinx/Vivado/2020.1/bin/xtclsh"
alias vivado="/opt/Xilinx/Vivado/2020.1/bin/vivado"
alias xelab="/opt/Xilinx/Vivado/2020.1/bin/xelab"
$ nano .bashrc
Paste this in it:
if [ -f ~/.aliases ]; then
. ~/.aliases
fi
$ nano .zshrc
Paste this in it:
source $HOME/.aliases
Restart the terminal for changes to take place before doing the next steps.
Step 3 - The command
You can use this small UVM example if you don’t have any UVM experience. After navigating to the example UVM SystemVerilog file in the terminal. Run the following commands:
$ xvlog –sv -L uvm uvm_basics_hello_world.sv
$ xelab top
$ xsim –R top
The name top is the top module name of the example file. Please change it if using a different file.
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This guide and the website seems crude. I will update it in some time. For queries if any, you may contact me on john@opencollectortech.com.
Thank you for your support!
Hello. If you like this template, I’d be happy to get a coffee donation :)
